1. Field of the Invention
The present invention relates to high-speed, synchronous data transfer operations, and particularly, to a single stage delay clock crossing buffer circuit for enabling data transfer operations from a device being clocked at one domain, to another device clocked at a same frequency, but out of phase.
2. Description of the Prior Art
In many digital systems, there are often used independent clocks to drive different functional circuits. For example, certain processing blocks, e.g., bus, memory, I/O, may all operate on independent clocks. In complex logic designs having multiple clock domains, it is frequently required that data be transferred from one such clock domain to another such clock domain. Various techniques for such transfer are known to those skilled in the art; the technique selected being dependent on latency requirements, whether the clock frequencies are similar, etc.
A clock-domain crossing occurs when a signal data clocked by a first clock, e.g. a data transmit clock, is sampled by a register clocked by a second clock, e.g., receive clock, that is asynchronous to the transmit clock. FIG. 1(a) illustrates a circuit structure according to the prior art that includes an electronic flip-flop device 112, e.g., a D-flip flop, which is clocked in clock domain 110 by CLOCK_A, the output of which is connected to the input of another flip-flop device 124 which is clocked in a second clock domain 120 by CLOCK_B. If CLOCK_A and CLOCK_B are guaranteed to be the same frequency, then these domains are not asynchronous to each other, and for some phase relationships between CLOCK_A and CLOCK_B, the data transfer will function correctly. However for some phase relationships between CLOCK_A and CLOCK_B, the data will transition at the input to the second flip-flop device such that the setup and/or hold time of the flip-flop is violated. That is, the data signal may change value very close to the edge of the receive Clock_B, causing the output of the sampling device enter a meta-stable state or latch an erroneous value. As a result, the circuit will fail for these cases.
FIG. 1(b) illustrates a circuit structure according to the prior art that includes a flip-flop device 132 which is clocked in clock domain 130 by CLOCK_A, the output of which is connected to the input of another flip-flop device 142 which is clocked in a second clock domain 140 by CLOCK_B. Whereas the flip-flop device 124 in FIG. 1(a) was clocked by the rising edge of CLOCK_B, the flip-flop device 142 in FIG. 1(b) is clocked by the falling edge of CLOCK_B. The output of flip-flop 142 connects to an additional flip-flop device 144 which is clocked by the rising edge of CLOCK_B, thus providing equivalent phase alignment for the two cases. As in the circuit of FIG. 1(a), the circuit of FIG. 1(b) will work for some phase relationships between the clocks and will fail for other phase relationships.
For example, assuming that in each case (FIGS. 1(a) and 1(b)) the propagation delay of data from the rising edge of CLOCK_A, through the first flip-flop device, to the input of the second flip-flop device is less than one half of the clock cycle. Then, the phase relationships for which the circuit in FIG. 1(a) fails are mutually exclusive with the phase relationships for which the circuit in FIG. 1(b) fails. Since the phase relationship between CLOCK_A and CLOCK_B is unknown, neither circuit in FIG. 1 may be used reliably.
To avoid unpredictable behavior this instability, circuits must be designed to properly synchronize all signals that cross clock domain.
One typical solution to the problem, when transferring data from one clock domain to another of the same frequency, a large clock crossing buffer is provided with a write and read pointer incrementing from the respective clocks through the buffers. This approach has a data delay directly associated with the number of buffers. For instance, assuming that data must be transferred continuously across this clock domain crossing, one such solution is to implement a First-In First-Out (FIFO) register file. Data is written to the FIFO synchronous to CLOCK_A, and is read from the FIFO synchronous to CLOCK_B. The write address and read address are initialized such that at any given moment the FIFO register being written is never the same as the FIFO register being read. While effective, this solution requires a FIFO register N-deep and n-bit wide register file, where n is the width of the data path, and N is typically greater than or equal to 4. This solution also introduces approximately N/2 clock cycles of latency into the data path.
It would thus be highly desirable to provide a circuit structure and method for transferring data from one clock domain to another clock domain where the two clock domains are of the same frequency, and have fixed but unknown phase relationship to each other.
It would thus be highly desirable to provide a circuit structure and method for transferring data from one clock domain to another utilizing one or two buffers without violating set up and hold times.